I. Field of the Invention
This invention relates to a method of manufacturing a semiconductor element such as a diode or transistor used with a semiconductor device.
II. Description of the Prior Art
The known method of manufacturing a plurality of semiconductor elements by sizing a semiconductor wafer includes the undermentioned method of RCA company (the U.S. Pat. No. 3,046,176). This U.S. patent method comprises the steps of forming a plurality of active elements in a semiconductor wafer 1; a selectively depositing ohmic electrodes on said active elements; dipping the mass in a bath of molten solder to coat a solder layer 3 on each of the ohmic electrodes 2 alone (FIG. 1(a)); dipping the mass in a wafer-etching solution with each solder layer 3 used as a mask; separating those portions of the wafer 1 which are interposed between the respective active elements by chemical etching. By these steps, a semiconductor element 4 comprising the solder layer 3 on each side of the semiconductor wafer 1 with the ohmic electrodes 2 each interposed between the solder layer 3 and semiconductor wafer 1 (FIG. 1(b)) is formed. However, the above-mentioned U.S. patent method has the following drawbacks:
(1) Due to a recent trend to enlarge semiconductor wafer, cracks are likely to arise in the wafer during its dipping in a solder bath. When dipped in a solder bath, a wafer having a larger diameter than 2 inches is subject to great thermal shocks, resulting in the damage of the wafer, the occurrence of cracks therein, a decline in the yield of a semiconductor device and the loss of its reliability.
(2) As seen from FIG. 1(b), a semiconductor element 4 produced has its solder layers 3 raised in the middle due to the surface tension of solder. Where the semiconductor element 4 is set between electrodes 5, then irregularities arise in the thickness of the solder layers 3 coated on both sides of the semiconductor element 4 as illustrated in FIG. 2(b). Further, stresses locally applied to the semiconductor element 4 when mounted between a pair of electrodes given rise to a decline in the property of said semiconductor element 4.
(3) When dipped in a solder bath, the semiconductor wafer 1 is adversely affected by the surface tension of the solder and thermal stresses exerted thereby, presenting difficulties in manufacturing a soldered semiconductor element having a prescribed total thickness.